From 3cb3f8d4b1d4697abe8b1dca75d7bc5d31fc2b82 Mon Sep 17 00:00:00 2001
From: Marco Thomas <github@marcothms.de>
Date: Tue, 13 May 2025 14:25:32 +0900
Subject: [PATCH] chore: Update comments

---
 src/instructions.rs | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/instructions.rs b/src/instructions.rs
index da97544..5861ded 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -5,7 +5,7 @@ pub type ImmediateWord = u16;
 
 #[derive(Debug, Clone)]
 #[allow(dead_code)]
-/// Can be used to encode either byte or word operands
+/// Encodes either Byte- or Word-sized operands.
 pub enum ImmediateOperand {
     Byte(ImmediateByte),
     Word(ImmediateWord),
@@ -23,7 +23,7 @@ impl fmt::Display for ImmediateOperand {
 #[derive(Debug, Clone)]
 #[allow(dead_code)]
 /// A single 'line' of executable ASM is called an Instruction, which
-/// contains the `Opcode` that will be executed, alongside its starting offset
+/// contains the `Mnemonic` that will be executed, alongside its starting offset
 /// and the raw parsed bytes
 pub struct Instruction {
     pub start: usize,     // location of the instruction start
@@ -53,7 +53,8 @@ impl fmt::Display for Instruction {
 
 #[derive(Debug, Clone)]
 #[allow(dead_code, non_camel_case_types)]
-/// All possible opcode variantions.
+/// All possible mnemonic variantions.
+/// These are sorted by type and are not in hex-encoding order.
 // XXX: convert this copy and paste horror in a proc macro like
 //      enum Opcode {
 //         #[derive(default_variations)]
@@ -185,9 +186,9 @@ impl fmt::Display for Mnemonic {
     }
 }
 
-/// Registers of a 8086 processor
 #[derive(Debug, Clone)]
 #[allow(dead_code)]
+/// Registers of a 8086 processor
 pub enum Register {
     // 8 bit
     // low bytes