From 48eeff16faf7199f9447c78001a8e789183c3f30 Mon Sep 17 00:00:00 2001 From: Marco Thomas Date: Tue, 20 May 2025 11:28:23 +0900 Subject: [PATCH] chore: align disasm print more with objdump(1) --- src/instructions.rs | 20 ++++++++++---------- src/register.rs | 40 ++++++++++++++++++++-------------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/instructions.rs b/src/instructions.rs index 85719c1..c6a9e2e 100644 --- a/src/instructions.rs +++ b/src/instructions.rs @@ -56,7 +56,7 @@ impl Instruction { impl fmt::Display for Instruction { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "{:04x}: ", self.start).unwrap(); + write!(f, "{:04x}:\t", self.start).unwrap(); write!( f, @@ -65,11 +65,11 @@ impl fmt::Display for Instruction { .iter() .map(|b| format!("{:02x}", b)) .collect::>() - .join("") + .join(" ") ) .unwrap(); - write!(f, "\t\t{}", self.opcode) + write!(f, "\t{}", self.opcode) } } @@ -529,14 +529,14 @@ impl fmt::Display for Mnemonic { Self::SAR_fromReg(target, reg) => write!(f, "sar {target}, {reg}"), Self::IN_AL(byte) => write!(f, "in {}, {byte:#04x}", Register::AL), - Self::IN_AX(byte) => write!(f, "in :#04x{}, {byte:#04x}", Register::AX), - Self::IN_ALDX => write!(f, "in {}, :#04x{}", Register::AL, Register::DX), - Self::IN_AXDX => write!(f, "in {}, :#04x{}", Register::AX, Register::DX), + Self::IN_AX(byte) => write!(f, "in {}, {byte:#04x}", Register::AX), + Self::IN_ALDX => write!(f, "in {}, {}", Register::AL, Register::DX), + Self::IN_AXDX => write!(f, "in {}, {}", Register::AX, Register::DX), - Self::OUT_AL(byte) => write!(f, "out :#04x{}, {byte:#04x}", Register::AL), - Self::OUT_AX(byte) => write!(f, "out :#04x{}, {byte:#04x}", Register::AX), - Self::OUT_ALDX => write!(f, "out {}, :#04x{}", Register::AL, Register::DX), - Self::OUT_AXDX => write!(f, "out {}, :#04x{}", Register::AX, Register::DX), + Self::OUT_AL(byte) => write!(f, "out {}, {byte:#04x}", Register::AL), + Self::OUT_AX(byte) => write!(f, "out {}, {byte:#04x}", Register::AX), + Self::OUT_ALDX => write!(f, "out {}, {}", Register::AL, Register::DX), + Self::OUT_AXDX => write!(f, "out {}, {}", Register::AX, Register::DX), Self::INT(byte) => write!(f, "int {byte:#04x}"), Self::INTO => write!(f, "into"), diff --git a/src/register.rs b/src/register.rs index 08c6c3a..a9d1d2e 100644 --- a/src/register.rs +++ b/src/register.rs @@ -66,22 +66,22 @@ impl Register { impl fmt::Display for Register { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { - Self::AX => write!(f, "ax"), - Self::BX => write!(f, "bx"), - Self::CX => write!(f, "cx"), - Self::DX => write!(f, "dx"), - Self::AH => write!(f, "ah"), - Self::AL => write!(f, "al"), - Self::BL => write!(f, "bl"), - Self::BH => write!(f, "bh"), - Self::CH => write!(f, "ch"), - Self::CL => write!(f, "cl"), - Self::DH => write!(f, "dh"), - Self::DL => write!(f, "dl"), - Self::DI => write!(f, "di"), - Self::SI => write!(f, "si"), - Self::BP => write!(f, "bp"), - Self::SP => write!(f, "sp"), + Self::AX => write!(f, "%ax"), + Self::BX => write!(f, "%bx"), + Self::CX => write!(f, "%cx"), + Self::DX => write!(f, "%dx"), + Self::AH => write!(f, "%ah"), + Self::AL => write!(f, "%al"), + Self::BL => write!(f, "%bl"), + Self::BH => write!(f, "%bh"), + Self::CH => write!(f, "%ch"), + Self::CL => write!(f, "%cl"), + Self::DH => write!(f, "%dh"), + Self::DL => write!(f, "%dl"), + Self::DI => write!(f, "%di"), + Self::SI => write!(f, "%si"), + Self::BP => write!(f, "%bp"), + Self::SP => write!(f, "%sp"), } } } @@ -113,10 +113,10 @@ impl SegmentRegister { impl fmt::Display for SegmentRegister { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { - Self::DS => write!(f, "ds"), - Self::ES => write!(f, "es"), - Self::SS => write!(f, "ss"), - Self::CS => write!(f, "cs"), + Self::DS => write!(f, "%ds"), + Self::ES => write!(f, "%es"), + Self::SS => write!(f, "%ss"), + Self::CS => write!(f, "%cs"), } } }