marcothms/8086-rs
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chore: fix byte/word size ambiguitis in disasm output

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Marco Thomas
2025-05-25 10:09:23 +09:00
parent 058afeb7ba
commit 90fb88aec6
1 changed files with 35 additions and 35 deletions
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70
src/instructions.rs
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@@ -33,7 +33,7 @@ impl fmt::Display for Instruction {
write!(
f,
"{:<10}",
"{:<16}", // length of longest possible instruction
self.raw
.iter()
.map(|b| format!("{:02x}", b))
@@ -301,8 +301,8 @@ impl fmt::Display for Mnemonic {
match self {
Self::ADD_FromReg(target, reg) => write!(f, "add {target}, {reg}"),
Self::ADD_ToReg(target, reg) => write!(f, "add {reg}, {target}"),
Self::ADD_Ib(target, byte) => write!(f, "add {target}, {byte:#04x}"),
Self::ADD_Iv(target, word) => write!(f, "add {target}, {word:#04x}"),
Self::ADD_Ib(target, byte) => write!(f, "add byte ptr {target}, {byte:#04x}"),
Self::ADD_Iv(target, word) => write!(f, "add word ptr {target}, {word:#04x}"),
Self::ADD_ALIb(byte) => write!(f, "add {}, {byte:#04x}", Register::AL),
Self::ADD_AXIv(word) => write!(f, "add {}, {word:#04x}", Register::AX),
@@ -316,29 +316,29 @@ impl fmt::Display for Mnemonic {
Self::OR_FromReg(target, reg) => write!(f, "or {target}, {reg}"),
Self::OR_ToReg(target, reg) => write!(f, "or {reg}, {target}"),
Self::OR_Ib(target, byte) => write!(f, "or {target}, {byte:#04x}"),
Self::OR_Iv(target, word) => write!(f, "or {target}, {word:#04x}"),
Self::OR_Ib(target, byte) => write!(f, "or byte ptr {target}, {byte:#04x}"),
Self::OR_Iv(target, word) => write!(f, "or word ptr {target}, {word:#04x}"),
Self::OR_ALIb(byte) => write!(f, "or {}, {byte:#04x}", Register::AL),
Self::OR_AXIv(word) => write!(f, "or {}, {word:#04x}", Register::AX),
Self::ADC_FromReg(target, reg) => write!(f, "adc {target}, {reg}"),
Self::ADC_ToReg(target, reg) => write!(f, "adc {reg}, {target}"),
Self::ADC_Ib(target, byte) => write!(f, "adc {target}, {byte:#04x}"),
Self::ADC_Iv(target, word) => write!(f, "adc {target}, {word:#04x}"),
Self::ADC_Ib(target, byte) => write!(f, "adc byte ptr {target}, {byte:#04x}"),
Self::ADC_Iv(target, word) => write!(f, "adc word ptr {target}, {word:#04x}"),
Self::ADC_ALIb(byte) => write!(f, "adc {}, {byte:#04x}", Register::AL),
Self::ADC_AXIv(word) => write!(f, "adc {}, {word:#04x}", Register::AX),
Self::SBB_FromReg(target, reg) => write!(f, "sbb {target}, {reg}"),
Self::SBB_ToReg(target, reg) => write!(f, "sbb {reg}, {target}"),
Self::SBB_Ib(target, byte) => write!(f, "sbb {target}, {byte:#04x}"),
Self::SBB_Iv(target, word) => write!(f, "sbb {target}, {word:#04x}"),
Self::SBB_Ib(target, byte) => write!(f, "sbb byte ptr {target}, {byte:#04x}"),
Self::SBB_Iv(target, word) => write!(f, "sbb word ptr {target}, {word:#04x}"),
Self::SBB_ALIb(byte) => write!(f, "sbb {}, {byte:#04x}", Register::AL),
Self::SBB_AXIv(word) => write!(f, "sbb {}, {word:#04x}", Register::AX),
Self::AND_FromReg(target, reg) => write!(f, "and {target}, {reg}"),
Self::AND_ToReg(target, reg) => write!(f, "and {reg}, {target}"),
Self::AND_Ib(target, byte) => write!(f, "and {target}, {byte:#04x}"),
Self::AND_Iv(target, word) => write!(f, "and {target}, {word:#04x}"),
Self::AND_Ib(target, byte) => write!(f, "and byte ptr {target}, {byte:#04x}"),
Self::AND_Iv(target, word) => write!(f, "and word ptr {target}, {word:#04x}"),
Self::AND_ALIb(byte) => write!(f, "and {}, {byte:#04x}", Register::AL),
Self::AND_AXIv(word) => write!(f, "and {}, {word:#04x}", Register::AX),
@@ -351,27 +351,27 @@ impl fmt::Display for Mnemonic {
Self::SUB_FromReg(target, reg) => write!(f, "sub {target}, {reg}"),
Self::SUB_ToReg(target, reg) => write!(f, "sub {reg}, {target}"),
Self::SUB_Ib(target, byte) => write!(f, "sub {target}, {byte:#04x}"),
Self::SUB_Iv(target, word) => write!(f, "sub {target}, {word:#04x}"),
Self::SUB_Ib(target, byte) => write!(f, "sub byte ptr {target}, {byte:#04x}"),
Self::SUB_Iv(target, word) => write!(f, "sub word ptr {target}, {word:#04x}"),
Self::SUB_ALIb(byte) => write!(f, "sub {}, {byte:#04x}", Register::AL),
Self::SUB_AXIv(word) => write!(f, "sub {}, {word:#04x}", Register::AX),
Self::XOR_FromReg(target, reg) => write!(f, "xor {target}, {reg}"),
Self::XOR_ToReg(target, reg) => write!(f, "xor {reg}, {target}"),
Self::XOR_Ib(target, byte) => write!(f, "xor {target}, {byte:#04x}"),
Self::XOR_Iv(target, word) => write!(f, "xor {target}, {word:#04x}"),
Self::XOR_Ib(target, byte) => write!(f, "xor byte ptr {target}, {byte:#04x}"),
Self::XOR_Iv(target, word) => write!(f, "xor word ptr {target}, {word:#04x}"),
Self::XOR_ALIb(byte) => write!(f, "xor {}, {byte:#04x}", Register::AL),
Self::XOR_AXIv(word) => write!(f, "xor {}, {word:#04x}", Register::AX),
Self::CMP_FromReg(target, reg) => write!(f, "cmp {target}, {reg}"),
Self::CMP_ToReg(target, reg) => write!(f, "cmp {reg}, {target}"),
Self::CMP_Ib(target, byte) => write!(f, "cmp {target}, {byte:#04x}"),
Self::CMP_Iv(target, word) => write!(f, "cmp {target}, {word:#04x}"),
Self::CMP_Ib(target, byte) => write!(f, "cmp byte ptr {target}, {byte:#04x}"),
Self::CMP_Iv(target, word) => write!(f, "cmp word ptr {target}, {word:#04x}"),
Self::CMP_ALIb(byte) => write!(f, "cmp {}, {byte:#04x}", Register::AL),
Self::CMP_AXIv(word) => write!(f, "cmp {}, {word:#04x}", Register::AX),
Self::INC_Reg(reg) => write!(f, "INC {reg}"),
Self::INC_Mod(target) => write!(f, "INC {target}"),
Self::INC_Reg(reg) => write!(f, "inc {reg}"),
Self::INC_Mod(target) => write!(f, "inc {target}"),
Self::DEC_Reg(reg) => write!(f, "dec {reg}"),
Self::DEC_Mod(target) => write!(f, "dec {target}"),
@@ -398,8 +398,8 @@ impl fmt::Display for Mnemonic {
Self::JCXZ(ibyte) => write!(f, "jcxz {ibyte:#04x}"),
Self::TEST(target, reg) => write!(f, "test {target}, {reg}"),
Self::TEST_Ib(target, byte) => write!(f, "test byte {target}, {byte:#04x}"),
Self::TEST_Iv(target, word) => write!(f, "test word {target}, {word:#04x}"),
Self::TEST_Ib(target, byte) => write!(f, "test byte ptr {target}, {byte:#04x}"),
Self::TEST_Iv(target, word) => write!(f, "test word ptr {target}, {word:#04x}"),
Self::TEST_ALIb(byte) => write!(f, "test {}, {byte:#04x}", Register::AL),
Self::TEST_AXIv(word) => write!(f, "test {}, {word:#04x}", Register::AX),
@@ -410,8 +410,8 @@ impl fmt::Display for Mnemonic {
Self::MOV_ToReg(target, reg) => write!(f, "mov {reg}, {target}"),
Self::MOV_FromSReg(target, reg) => write!(f, "mov {target}, {reg}"),
Self::MOV_ToSReg(target, reg) => write!(f, "mov {reg}, {target}"),
Self::MOV_Ib(target, byte) => write!(f, "mov {target}, {byte:#04x}"),
Self::MOV_Iv(target, word) => write!(f, "mov {target}, {word:#04x}"),
Self::MOV_Ib(target, byte) => write!(f, "mov byte {target}, {byte:#04x}"),
Self::MOV_Iv(target, word) => write!(f, "mov word {target}, {word:#04x}"),
Self::MOV_AL0b(byte) => write!(f, "mov {}, {byte:#04x}", Register::AL),
Self::MOV_AX0v(word) => write!(f, "mov {}, {word:#04x}", Register::AX),
@@ -484,15 +484,15 @@ impl fmt::Display for Mnemonic {
Self::DIV(target) => write!(f, "mdiv {target}"),
Self::IDIV(target) => write!(f, "idiv {target}"),
Self::HLT => write!(f, "HLT"),
Self::HLT => write!(f, "hlt"),
Self::ROL_b(target, byte) => write!(f, "rol {target}, {byte:#04x}"),
Self::ROR_b(target, byte) => write!(f, "ror {target}, {byte:#04x}"),
Self::RCL_b(target, byte) => write!(f, "rcl {target}, {byte:#04x}"),
Self::RCR_b(target, byte) => write!(f, "rcr {target}, {byte:#04x}"),
Self::SHL_b(target, byte) => write!(f, "shl {target}, {byte:#04x}"),
Self::SHR_b(target, byte) => write!(f, "shr {target}, {byte:#04x}"),
Self::SAR_b(target, byte) => write!(f, "sar {target}, {byte:#04x}"),
Self::ROL_b(target, byte) => write!(f, "rol byte {target}, {byte:#04x}"),
Self::ROR_b(target, byte) => write!(f, "ror byte {target}, {byte:#04x}"),
Self::RCL_b(target, byte) => write!(f, "rcl byte {target}, {byte:#04x}"),
Self::RCR_b(target, byte) => write!(f, "rcr byte {target}, {byte:#04x}"),
Self::SHL_b(target, byte) => write!(f, "shl byte {target}, {byte:#04x}"),
Self::SHR_b(target, byte) => write!(f, "shr byte {target}, {byte:#04x}"),
Self::SAR_b(target, byte) => write!(f, "sar byte {target}, {byte:#04x}"),
Self::ROL_fromReg(target, reg) => write!(f, "rol {target}, {reg}"),
Self::ROR_fromReg(target, reg) => write!(f, "ror {target}, {reg}"),
Self::RCL_fromReg(target, reg) => write!(f, "rcl {target}, {reg}"),
@@ -501,13 +501,13 @@ impl fmt::Display for Mnemonic {
Self::SHR_fromReg(target, reg) => write!(f, "shr {target}, {reg}"),
Self::SAR_fromReg(target, reg) => write!(f, "sar {target}, {reg}"),
Self::IN_AL(byte) => write!(f, "in {}, {byte:#04x}", Register::AL),
Self::IN_AX(byte) => write!(f, "in {}, {byte:#04x}", Register::AX),
Self::IN_AL(byte) => write!(f, "in byte {}, {byte:#04x}", Register::AL),
Self::IN_AX(byte) => write!(f, "in byte {}, {byte:#04x}", Register::AX),
Self::IN_ALDX => write!(f, "in {}, {}", Register::AL, Register::DX),
Self::IN_AXDX => write!(f, "in {}, {}", Register::AX, Register::DX),
Self::OUT_AL(byte) => write!(f, "out {}, {byte:#04x}", Register::AL),
Self::OUT_AX(byte) => write!(f, "out {}, {byte:#04x}", Register::AX),
Self::OUT_AL(byte) => write!(f, "out byte {}, {byte:#04x}", Register::AL),
Self::OUT_AX(byte) => write!(f, "out byte {}, {byte:#04x}", Register::AX),
Self::OUT_ALDX => write!(f, "out {}, {}", Register::AL, Register::DX),
Self::OUT_AXDX => write!(f, "out {}, {}", Register::AX, Register::DX),