ft: fixed modrm target calculation
While implementing some more mnemonics and testing them, it was clear that modrm parsing was wrong. Now reg to reg and immediates, together with GPR1 interpretation should work as expected. GPR1 interpretation can currently not be merged into the modrm function, as with the current abstraction the REG needs to select the correct mnemonic, for which we need to also know the second operand, which will only be parsed afterwards. But this will be incorporated at some point, this just marks the first working state.
This commit is contained in:
288
src/disasm.rs
288
src/disasm.rs
@@ -2,12 +2,12 @@ use core::fmt;
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use std::{fs::File, io::Read, process::exit};
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use crate::aout::Aout;
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use crate::instructions::{Displacement, MemoryIndex, RegisterId, SegmentRegister};
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use crate::modrm;
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use crate::instructions::{MemoryIndex, ModRmTarget, OperandSize, RegisterId, SegmentRegister};
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use crate::{
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Args,
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instructions::{ImmediateByte, ImmediateWord, Instruction, Opcode, Register},
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instructions::{ImmediateByte, ImmediateWord, Instruction, Mnemonic, Register},
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};
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use crate::{modrmb, modrms, modrmv};
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#[derive(Debug)]
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/// Generic errors, which are encountered during parsing.
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@@ -78,8 +78,6 @@ impl Disassembler {
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// advance to operand
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self.offset += 1;
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let byte = self.text[self.offset];
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// jump to right after operand
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self.offset += 1;
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self.instruction.raw.push(byte);
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byte
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}
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@@ -91,51 +89,69 @@ impl Disassembler {
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self.offset += 1;
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let byte1 = self.text[self.offset];
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let byte2 = self.text[self.offset + 1];
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// jump right after operand
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self.offset += 2;
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// jump onto last operand
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self.offset += 1;
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self.instruction.raw.push(byte1);
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self.instruction.raw.push(byte2);
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u16::from_le_bytes([byte1, byte2])
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}
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/// Takes in a modrm byte and returns mod, reg and r/m.
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fn deconstruct_modrm_byte(modrm: u8) -> (u8, u8, u8) {
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let mode = (modrm >> 6) & 0b11;
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let reg = (modrm >> 3) & 0b111;
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let rm = modrm & 0b111;
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(mode, reg, rm)
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}
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/// Parse a single modrm byte, return the resulting MemoryIndex and advance the offset.
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/// Returns the parsed modrm memory access and the source register
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pub fn parse_modrm_byte(&mut self) -> (MemoryIndex, RegisterId) {
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/// Returns the parsed modrm target and the source register
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pub fn parse_modrm_byte(&mut self, size: OperandSize) -> (ModRmTarget, RegisterId) {
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// advance to operand
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self.offset += 1;
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let modrm = self.text[self.offset];
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self.instruction.raw.push(modrm);
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// jump right after operand
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self.offset += 1;
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// Calculate ModRM byte with bitmask
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let modulo = modrm >> 6;
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let reg_id = (modrm >> 3) & 7;
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let rm = modrm & 7;
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let (mode, reg, rm) = Self::deconstruct_modrm_byte(modrm);
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let displacement = match modulo {
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log::debug!(
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"0x{:04x} deconstructed into: 0b{:b}, 0b{:b}, 0b{:b}",
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modrm,
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mode,
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reg,
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rm
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);
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let mut displacement = None;
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match mode {
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0b00 => {
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if rm == 0b110 {
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log::debug!("Additional word during ModRM parsing was read with mod 0.");
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Some(Displacement::Word(self.parse_word()))
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displacement = Some(OperandSize::Word(self.parse_word()));
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} else {
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None
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displacement = None;
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}
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}
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0b01 => {
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log::debug!("Additional byte during ModRM parsing was read.");
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Some(Displacement::Byte(self.parse_byte()))
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displacement = Some(OperandSize::Byte(self.parse_byte()))
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}
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0b10 => {
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log::debug!("Additional word during ModRM parsing was read.");
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Some(Displacement::Word(self.parse_word()))
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displacement = Some(OperandSize::Word(self.parse_word()));
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}
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0b11 => {
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// XXX is this correct?
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log::debug!(
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"No displacement, as reg to reg - maybe some implementation is missing here"
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);
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None
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log::debug!("ModRM to reg");
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let target = match size {
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OperandSize::Byte(_) => {
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ModRmTarget::Register(Register::by_id(OperandSize::Byte(rm)))
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}
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OperandSize::Word(_) => {
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ModRmTarget::Register(Register::by_id(OperandSize::Word(rm.into())))
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}
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};
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return (target, reg);
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}
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_ => panic!("Invalid ModRM byte encountered"),
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};
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@@ -184,7 +200,35 @@ impl Disassembler {
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_ => panic!("Invalid ModRM byte encountered"),
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};
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(index, reg_id)
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(ModRmTarget::Memory(index), reg)
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}
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/// Match the modrm reg bits to the GPR1 mnemonics.
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pub fn modrm_reg_to_mnemonic(reg: u8, target: ModRmTarget, imm: OperandSize) -> Mnemonic {
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match imm {
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OperandSize::Byte(b) => match reg {
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0b000 => Mnemonic::ADD_Ib(target, ImmediateByte(b)),
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0b001 => Mnemonic::OR_Ib(target, ImmediateByte(b)),
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0b010 => Mnemonic::ADC_Ib(target, ImmediateByte(b)),
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0b011 => Mnemonic::SBB_Ib(target, ImmediateByte(b)),
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0b100 => Mnemonic::AND_Ib(target, ImmediateByte(b)),
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0b101 => Mnemonic::SUB_Ib(target, ImmediateByte(b)),
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0b110 => Mnemonic::XOR_Ib(target, ImmediateByte(b)),
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0b111 => Mnemonic::CMP_Ib(target, ImmediateByte(b)),
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_ => panic!("Illegal GPR1 mnemonic"),
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},
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OperandSize::Word(w) => match reg {
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0b000 => Mnemonic::ADD_Iv(target, ImmediateWord(w)),
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0b001 => Mnemonic::OR_Iv(target, ImmediateWord(w)),
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0b010 => Mnemonic::ADC_Iv(target, ImmediateWord(w)),
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0b011 => Mnemonic::SBB_Iv(target, ImmediateWord(w)),
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0b100 => Mnemonic::AND_Iv(target, ImmediateWord(w)),
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0b101 => Mnemonic::SUB_Iv(target, ImmediateWord(w)),
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0b110 => Mnemonic::XOR_Iv(target, ImmediateWord(w)),
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0b111 => Mnemonic::CMP_Iv(target, ImmediateWord(w)),
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_ => panic!("Illegal GPR1 mnemonic"),
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},
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}
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}
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/// Decode instructions from the text section of the provided binary
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@@ -204,30 +248,177 @@ impl Disassembler {
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// additional raw bytes will be pushed by parse functions
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self.instruction.raw.push(opcode);
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// XXX: convert this copy and paste horror into a proc macro
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self.instruction.opcode = match opcode {
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// ADD
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0x00 => modrm!(self, ADD_EbGb),
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0x01 => modrm!(self, ADD_EvGv),
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0x02 => modrm!(self, ADD_GbEb),
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0x03 => modrm!(self, ADD_GvEv),
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0x04 => Opcode::ADD_ALIb(ImmediateByte(self.parse_byte())),
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0x05 => Opcode::ADD_AXIv(ImmediateWord(self.parse_word())),
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// PUSH
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0x06 => Opcode::PUSH(SegmentRegister::by_id(self.parse_modrm_byte().1)),
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// POP
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0x07 => Opcode::POP(SegmentRegister::by_id(self.parse_modrm_byte().1)),
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// OR
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0x08 => modrm!(self, OR_EbGb),
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0x0A => modrm!(self, OR_GbEb),
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// INT
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0xCD => Opcode::INT(ImmediateByte(self.parse_byte())),
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// MOV
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0xBB => Opcode::MOV_BXIv(ImmediateWord(self.parse_word())),
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0x00 => modrmb!(self, ADD_FromReg),
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0x01 => modrmv!(self, ADD_FromReg),
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0x02 => modrmb!(self, ADD_ToReg),
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0x03 => modrmv!(self, ADD_ToReg),
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0x04 => Mnemonic::ADD_ALIb(ImmediateByte(self.parse_byte())),
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0x05 => Mnemonic::ADD_AXIv(ImmediateWord(self.parse_word())),
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0x06 => Mnemonic::PUSH_S(SegmentRegister::ES),
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0x07 => Mnemonic::POP_S(SegmentRegister::ES),
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0x08 => modrmb!(self, OR_FromReg),
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0x09 => modrmv!(self, OR_FromReg),
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0x0A => modrmb!(self, OR_ToReg),
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0x0B => modrmv!(self, OR_ToReg),
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0x0C => Mnemonic::OR_ALIb(ImmediateByte(self.parse_byte())),
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0x0D => Mnemonic::OR_AXIv(ImmediateWord(self.parse_word())),
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0x0E => Mnemonic::PUSH_S(SegmentRegister::CS),
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0x0F => panic!("Opcode 0x0F (POP CS) is considered undefined"),
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0x10 => modrmb!(self, ADC_FromReg),
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0x11 => modrmv!(self, ADC_FromReg),
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0x12 => modrmb!(self, ADC_ToReg),
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0x13 => modrmv!(self, ADC_ToReg),
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0x14 => Mnemonic::ADC_ALIb(ImmediateByte(self.parse_byte())),
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0x15 => Mnemonic::ADC_AXIv(ImmediateWord(self.parse_word())),
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0x16 => Mnemonic::PUSH_S(SegmentRegister::SS),
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0x17 => Mnemonic::POP_S(SegmentRegister::SS),
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0x18 => modrmb!(self, SBB_FromReg),
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0x19 => modrmv!(self, SBB_FromReg),
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0x1A => modrmb!(self, SBB_ToReg),
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0x1B => modrmv!(self, SBB_ToReg),
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0x1C => Mnemonic::SBB_ALIb(ImmediateByte(self.parse_byte())),
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0x1D => Mnemonic::SBB_AXIv(ImmediateWord(self.parse_word())),
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0x1E => Mnemonic::PUSH_S(SegmentRegister::DS),
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0x1F => Mnemonic::POP_S(SegmentRegister::DS),
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0x20 => modrmb!(self, AND_FromReg),
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0x21 => modrmv!(self, AND_FromReg),
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0x22 => modrmb!(self, AND_ToReg),
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0x23 => modrmv!(self, AND_ToReg),
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0x24 => Mnemonic::AND_ALIb(ImmediateByte(self.parse_byte())),
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0x25 => Mnemonic::AND_AXIv(ImmediateWord(self.parse_word())),
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0x26 => Mnemonic::OVERRIDE(SegmentRegister::ES),
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0x27 => Mnemonic::DAA,
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0x28 => modrmb!(self, SUB_FromReg),
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0x29 => modrmv!(self, SUB_FromReg),
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0x2A => modrmb!(self, SUB_ToReg),
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0x2B => modrmv!(self, SUB_ToReg),
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0x2C => Mnemonic::SUB_ALIb(ImmediateByte(self.parse_byte())),
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0x2D => Mnemonic::SUB_AXIv(ImmediateWord(self.parse_word())),
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0x2E => Mnemonic::OVERRIDE(SegmentRegister::CS),
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0x2F => Mnemonic::DAS,
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0x30 => modrmb!(self, XOR_FromReg),
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0x31 => modrmv!(self, XOR_FromReg),
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0x32 => modrmb!(self, XOR_ToReg),
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0x33 => modrmv!(self, XOR_ToReg),
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0x34 => Mnemonic::XOR_ALIb(ImmediateByte(self.parse_byte())),
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0x35 => Mnemonic::XOR_AXIv(ImmediateWord(self.parse_word())),
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0x36 => Mnemonic::OVERRIDE(SegmentRegister::SS),
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0x37 => Mnemonic::AAA,
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0x38 => modrmb!(self, CMP_FromReg),
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0x39 => modrmv!(self, CMP_FromReg),
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0x3A => modrmb!(self, CMP_ToReg),
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0x3B => modrmv!(self, CMP_ToReg),
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0x3C => Mnemonic::CMP_ALIb(ImmediateByte(self.parse_byte())),
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0x3D => Mnemonic::CMP_AXIv(ImmediateWord(self.parse_word())),
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0x3E => Mnemonic::OVERRIDE(SegmentRegister::DS),
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0x3F => Mnemonic::AAS,
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0x40 => Mnemonic::INC(Register::AX),
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0x41 => Mnemonic::INC(Register::CX),
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0x42 => Mnemonic::INC(Register::DX),
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0x43 => Mnemonic::INC(Register::BX),
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0x44 => Mnemonic::INC(Register::SP),
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0x45 => Mnemonic::INC(Register::BP),
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0x46 => Mnemonic::INC(Register::SI),
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0x47 => Mnemonic::INC(Register::DI),
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0x48 => Mnemonic::DEC(Register::AX),
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0x49 => Mnemonic::DEC(Register::CX),
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0x4A => Mnemonic::DEC(Register::DX),
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0x4B => Mnemonic::DEC(Register::BX),
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0x4C => Mnemonic::DEC(Register::SP),
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0x4D => Mnemonic::DEC(Register::BP),
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0x4E => Mnemonic::DEC(Register::SI),
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0x4F => Mnemonic::DEC(Register::DI),
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0x50 => Mnemonic::PUSH_R(Register::AX),
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0x51 => Mnemonic::PUSH_R(Register::CX),
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0x52 => Mnemonic::PUSH_R(Register::DX),
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0x53 => Mnemonic::PUSH_R(Register::BX),
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0x54 => Mnemonic::PUSH_R(Register::SP),
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0x55 => Mnemonic::PUSH_R(Register::BP),
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0x56 => Mnemonic::PUSH_R(Register::SI),
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0x57 => Mnemonic::PUSH_R(Register::DI),
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0x58 => Mnemonic::POP_R(Register::AX),
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0x59 => Mnemonic::POP_R(Register::CX),
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0x5A => Mnemonic::POP_R(Register::DX),
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0x5B => Mnemonic::POP_R(Register::BX),
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0x5C => Mnemonic::POP_R(Register::SP),
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0x5D => Mnemonic::POP_R(Register::BP),
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0x5E => Mnemonic::POP_R(Register::SI),
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0x5F => Mnemonic::POP_R(Register::DI),
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0x60..=0x6F => panic!("0x06 to 0x06F is considered undefined."),
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0x70 => Mnemonic::JO(ImmediateByte(self.parse_byte())),
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0x71 => Mnemonic::JNO(ImmediateByte(self.parse_byte())),
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0x72 => Mnemonic::JB(ImmediateByte(self.parse_byte())),
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0x73 => Mnemonic::JNB(ImmediateByte(self.parse_byte())),
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0x74 => Mnemonic::JZ(ImmediateByte(self.parse_byte())),
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0x75 => Mnemonic::JNZ(ImmediateByte(self.parse_byte())),
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0x76 => Mnemonic::JBE(ImmediateByte(self.parse_byte())),
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0x77 => Mnemonic::JA(ImmediateByte(self.parse_byte())),
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0x78 => Mnemonic::JS(ImmediateByte(self.parse_byte())),
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0x79 => Mnemonic::JNS(ImmediateByte(self.parse_byte())),
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0x7A => Mnemonic::JPE(ImmediateByte(self.parse_byte())),
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0x7B => Mnemonic::JPO(ImmediateByte(self.parse_byte())),
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0x7C => Mnemonic::JL(ImmediateByte(self.parse_byte())),
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0x7D => Mnemonic::JGE(ImmediateByte(self.parse_byte())),
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0x7E => Mnemonic::JLE(ImmediateByte(self.parse_byte())),
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0x7F => Mnemonic::JG(ImmediateByte(self.parse_byte())),
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// 0x80..=0x83 => panic!("GRP1 not implemented"),
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0x80 => {
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let (target, reg) = self.parse_modrm_byte(OperandSize::Byte(0));
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let imm = self.parse_byte();
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Self::modrm_reg_to_mnemonic(reg, target, OperandSize::Byte(imm))
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}
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0x81 => {
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let (target, reg) = self.parse_modrm_byte(OperandSize::Word(0));
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let imm = self.parse_word();
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Self::modrm_reg_to_mnemonic(reg, target, OperandSize::Word(imm))
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}
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0x82 => panic!("Same as 0x80"),
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0x83 => panic!("Sign extented GPR1 not yet implemented"),
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0x84 => modrmb!(self, TEST),
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0x85 => modrmv!(self, TEST),
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0x86 => modrmb!(self, XHCG),
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0x87 => modrmv!(self, XHCG),
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0x88 => modrmb!(self, MOV_FromReg),
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0x89 => modrmv!(self, MOV_FromReg),
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0x8A => modrmb!(self, MOV_ToReg),
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0x8B => modrmv!(self, MOV_ToReg),
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0x8C => modrms!(self, MOV_FromSReg),
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0x8E => modrms!(self, MOV_ToSReg),
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0x8D => modrmv!(self, LEA),
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0xCD => Mnemonic::INT(ImmediateByte(self.parse_byte())),
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0xBB => Mnemonic::MOV_BXIv(ImmediateWord(self.parse_word())),
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_ => {
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eprintln!(
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"Encountered unknown self.instructionuction '0x{:x}'",
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opcode
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);
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eprintln!("Encountered unknown instruction '0x{:x}'", opcode);
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eprintln!("Offset might be misaligned and data is being interpreted.");
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eprintln!("Existing to avoid further misinterpretation...");
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exit(1);
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@@ -237,6 +428,7 @@ impl Disassembler {
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println!("{}", self.instruction);
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instructions.push(self.instruction.clone());
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self.instruction = Instruction::new();
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self.offset += 1;
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}
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Ok(instructions)
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@@ -1,8 +1,26 @@
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#[macro_export]
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/// Generate an Opcode for 'normal' ModRM instructions with mem access and a reg
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macro_rules! modrm {
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/// Generate a byte Opcode for 'normal' ModRM instructions with mem access and a reg
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macro_rules! modrmb {
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($self:ident, $variant:ident) => {{
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let (idx, reg) = $self.parse_modrm_byte();
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Opcode::$variant(idx, Register::by_id(reg))
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let (target, reg) = $self.parse_modrm_byte(OperandSize::Byte(0));
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Mnemonic::$variant(target, Register::by_id(OperandSize::Byte(reg)))
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}};
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}
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#[macro_export]
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/// Generate a word Opcode for 'normal' ModRM instructions with mem access and a reg
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macro_rules! modrmv {
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($self:ident, $variant:ident) => {{
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let (target, reg) = $self.parse_modrm_byte(OperandSize::Word(0));
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Mnemonic::$variant(target, Register::by_id(OperandSize::Word(reg.into())))
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||||
}};
|
||||
}
|
||||
|
||||
#[macro_export]
|
||||
/// Generate a word Opcode for 'normal' ModRM instructions with mem access and a segment reg
|
||||
macro_rules! modrms {
|
||||
($self:ident, $variant:ident) => {{
|
||||
let (target, reg) = $self.parse_modrm_byte(OperandSize::Word(0));
|
||||
Mnemonic::$variant(target, SegmentRegister::by_id(reg))
|
||||
}};
|
||||
}
|
||||
|
||||
@@ -12,9 +12,9 @@ pub type w = u16;
|
||||
/// contains the `Opcode` that will be executed, alongside its starting offset
|
||||
/// and the raw parsed bytes
|
||||
pub struct Instruction {
|
||||
pub start: usize, // location of the instruction start
|
||||
pub raw: Vec<u8>, // raw value of instruction
|
||||
pub opcode: Opcode, // actual instruction
|
||||
pub start: usize, // location of the instruction start
|
||||
pub raw: Vec<u8>, // raw value of instruction
|
||||
pub opcode: Mnemonic, // actual instruction
|
||||
}
|
||||
|
||||
impl Instruction {
|
||||
@@ -22,7 +22,7 @@ impl Instruction {
|
||||
Instruction {
|
||||
start: 0,
|
||||
raw: Vec::new(),
|
||||
opcode: Opcode::NOP(),
|
||||
opcode: Mnemonic::NOP(),
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -39,61 +39,163 @@ impl fmt::Display for Instruction {
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
#[allow(dead_code, non_camel_case_types)]
|
||||
pub enum Opcode {
|
||||
/// All possible opcode variantions.
|
||||
// XXX: convert this copy and paste horror in a proc macro like
|
||||
// enum Opcode {
|
||||
// #[derive(default_variations)]
|
||||
// ADD,
|
||||
// ...
|
||||
// }
|
||||
// which then add all variants and also create the matching logic for
|
||||
// src/disasm.rs decode_instructions()
|
||||
pub enum Mnemonic {
|
||||
NOP(),
|
||||
// ADD
|
||||
ADD_EbGb(MemoryIndex, Register),
|
||||
ADD_EvGv(MemoryIndex, Register),
|
||||
ADD_GbEb(MemoryIndex, Register),
|
||||
ADD_GvEv(MemoryIndex, Register),
|
||||
ADD_FromReg(ModRmTarget, Register),
|
||||
ADD_ToReg(ModRmTarget, Register),
|
||||
ADD_Ib(ModRmTarget, ImmediateByte),
|
||||
ADD_Iv(ModRmTarget, ImmediateWord),
|
||||
ADD_ALIb(ImmediateByte),
|
||||
ADD_AXIv(ImmediateWord),
|
||||
// PUSH
|
||||
PUSH(SegmentRegister),
|
||||
PUSH_R(Register),
|
||||
PUSH_S(SegmentRegister),
|
||||
// POP
|
||||
POP(SegmentRegister),
|
||||
POP_S(SegmentRegister),
|
||||
POP_R(Register),
|
||||
// OR
|
||||
OR_EbGb(MemoryIndex, Register),
|
||||
OR_GbEb(MemoryIndex, Register),
|
||||
OR_FromReg(ModRmTarget, Register),
|
||||
OR_ToReg(ModRmTarget, Register),
|
||||
OR_Ib(ModRmTarget, ImmediateByte),
|
||||
OR_Iv(ModRmTarget, ImmediateWord),
|
||||
OR_ALIb(ImmediateByte),
|
||||
OR_AXIv(ImmediateWord),
|
||||
// ADC
|
||||
ADC_FromReg(ModRmTarget, Register),
|
||||
ADC_ToReg(ModRmTarget, Register),
|
||||
ADC_Ib(ModRmTarget, ImmediateByte),
|
||||
ADC_Iv(ModRmTarget, ImmediateWord),
|
||||
ADC_ALIb(ImmediateByte),
|
||||
ADC_AXIv(ImmediateWord),
|
||||
// SBB
|
||||
SBB_FromReg(ModRmTarget, Register),
|
||||
SBB_ToReg(ModRmTarget, Register),
|
||||
SBB_Ib(ModRmTarget, ImmediateByte),
|
||||
SBB_Iv(ModRmTarget, ImmediateWord),
|
||||
SBB_ALIb(ImmediateByte),
|
||||
SBB_AXIv(ImmediateWord),
|
||||
// AND
|
||||
AND_FromReg(ModRmTarget, Register),
|
||||
AND_ToReg(ModRmTarget, Register),
|
||||
AND_Ib(ModRmTarget, ImmediateByte),
|
||||
AND_Iv(ModRmTarget, ImmediateWord),
|
||||
AND_ALIb(ImmediateByte),
|
||||
AND_AXIv(ImmediateWord),
|
||||
// Override
|
||||
OVERRIDE(SegmentRegister),
|
||||
// Decimal Adjustment
|
||||
DAA,
|
||||
DAS,
|
||||
AAA,
|
||||
AAS,
|
||||
// SUB
|
||||
SUB_FromReg(ModRmTarget, Register),
|
||||
SUB_ToReg(ModRmTarget, Register),
|
||||
SUB_Ib(ModRmTarget, ImmediateByte),
|
||||
SUB_Iv(ModRmTarget, ImmediateWord),
|
||||
SUB_ALIb(ImmediateByte),
|
||||
SUB_AXIv(ImmediateWord),
|
||||
// XOR
|
||||
XOR_FromReg(ModRmTarget, Register),
|
||||
XOR_ToReg(ModRmTarget, Register),
|
||||
XOR_Ib(ModRmTarget, ImmediateByte),
|
||||
XOR_Iv(ModRmTarget, ImmediateWord),
|
||||
XOR_ALIb(ImmediateByte),
|
||||
XOR_AXIv(ImmediateWord),
|
||||
// CMP
|
||||
CMP_FromReg(ModRmTarget, Register),
|
||||
CMP_ToReg(ModRmTarget, Register),
|
||||
CMP_Ib(ModRmTarget, ImmediateByte),
|
||||
CMP_Iv(ModRmTarget, ImmediateWord),
|
||||
CMP_ALIb(ImmediateByte),
|
||||
CMP_AXIv(ImmediateWord),
|
||||
// INC
|
||||
INC(Register),
|
||||
// DEC
|
||||
DEC(Register),
|
||||
// Jumps
|
||||
JO(ImmediateByte),
|
||||
JNO(ImmediateByte),
|
||||
JB(ImmediateByte),
|
||||
JNB(ImmediateByte),
|
||||
JZ(ImmediateByte),
|
||||
JNZ(ImmediateByte),
|
||||
JBE(ImmediateByte),
|
||||
JA(ImmediateByte),
|
||||
JS(ImmediateByte),
|
||||
JNS(ImmediateByte),
|
||||
JPE(ImmediateByte),
|
||||
JPO(ImmediateByte),
|
||||
JL(ImmediateByte),
|
||||
JGE(ImmediateByte),
|
||||
JLE(ImmediateByte),
|
||||
JG(ImmediateByte),
|
||||
// TEST
|
||||
TEST(ModRmTarget, Register),
|
||||
//XHCG
|
||||
XHCG(ModRmTarget, Register),
|
||||
// MOV
|
||||
MOV_FromReg(ModRmTarget, Register),
|
||||
MOV_ToReg(ModRmTarget, Register),
|
||||
MOV_FromSReg(ModRmTarget, SegmentRegister),
|
||||
MOV_ToSReg(ModRmTarget, SegmentRegister),
|
||||
MOV_BXIv(ImmediateWord),
|
||||
// LEA
|
||||
LEA(ModRmTarget, Register),
|
||||
// INT
|
||||
INT(ImmediateByte),
|
||||
// MOV
|
||||
MOV_BXIv(ImmediateWord),
|
||||
}
|
||||
|
||||
impl fmt::Display for Opcode {
|
||||
impl fmt::Display for Mnemonic {
|
||||
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
||||
match self {
|
||||
Self::INT(byte) => write!(f, "INT, {:x}", byte),
|
||||
Self::ADD_EbGb(mem, reg) => write!(f, "ADD {}, {}", mem, reg),
|
||||
Self::ADD_GbEb(mem, reg) => write!(f, "ADD {}, {}", reg, mem),
|
||||
Self::ADD_FromReg(mem, reg) => write!(f, "ADD {}, {}", mem, reg),
|
||||
Self::ADD_ToReg(mem, reg) => write!(f, "ADD {}, {}", reg, mem),
|
||||
Self::CMP_Iv(mem, imm) => write!(f, "CMP {}, {:04x}", mem, imm),
|
||||
Self::LEA(mem, reg) => write!(f, "LEA {}, {}", reg, mem),
|
||||
Self::MOV_BXIv(word) => write!(f, "MOV BX, {:04x}", word),
|
||||
_ => write!(f, "display not yet implemented"),
|
||||
Self::XOR_FromReg(mem, reg) => write!(f, "XOR {}, {}", mem, reg),
|
||||
_ => write!(f, "??? ??, ??"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Registers of a 8086 processor
|
||||
/// -x are 16bit, -l are 8bit
|
||||
#[derive(Debug, Clone)]
|
||||
#[allow(dead_code)]
|
||||
pub enum Register {
|
||||
AX,
|
||||
BX,
|
||||
CX,
|
||||
DX,
|
||||
AH,
|
||||
// 8 bit
|
||||
// low bytes
|
||||
AL,
|
||||
BL,
|
||||
BH,
|
||||
CH,
|
||||
CL,
|
||||
DH,
|
||||
DL,
|
||||
DI,
|
||||
SI,
|
||||
BP,
|
||||
SP,
|
||||
BL,
|
||||
// high bytes
|
||||
AH,
|
||||
CH,
|
||||
DH,
|
||||
BH,
|
||||
|
||||
// 16 bit
|
||||
AX, // accumulator
|
||||
CX, // counter
|
||||
DX, // data
|
||||
BX, // base
|
||||
SP, // stack pointer
|
||||
BP, // base pointer
|
||||
SI, // source index
|
||||
DI, // base index
|
||||
}
|
||||
|
||||
/// Selector for Register or Segment Register
|
||||
@@ -102,25 +204,30 @@ pub type RegisterId = u8;
|
||||
#[allow(dead_code)]
|
||||
impl Register {
|
||||
/// Find the register corresponding to the 8086 bytecode ID
|
||||
pub fn by_id(id: RegisterId) -> Self {
|
||||
pub fn by_id(id: OperandSize) -> Self {
|
||||
match id {
|
||||
0x00 => Self::AL,
|
||||
0x01 => Self::CL,
|
||||
0x02 => Self::DL,
|
||||
0x03 => Self::BL,
|
||||
0x04 => Self::AH,
|
||||
0x05 => Self::CH,
|
||||
0x06 => Self::DH,
|
||||
0x07 => Self::BH,
|
||||
0x10 => Self::AX,
|
||||
0x11 => Self::CX,
|
||||
0x12 => Self::DX,
|
||||
0x13 => Self::BX,
|
||||
0x14 => Self::SP,
|
||||
0x15 => Self::BP,
|
||||
0x16 => Self::SI,
|
||||
0x17 => Self::DI,
|
||||
_ => panic!("Invalid register ID encountered"),
|
||||
OperandSize::Byte(b) => match b {
|
||||
0b000 => Self::AL,
|
||||
0b001 => Self::CL,
|
||||
0b010 => Self::DL,
|
||||
0b011 => Self::BL,
|
||||
0b100 => Self::AH,
|
||||
0b101 => Self::CH,
|
||||
0b110 => Self::DH,
|
||||
0b111 => Self::BH,
|
||||
_ => panic!("Invalid 8bit register ID encountered"),
|
||||
},
|
||||
OperandSize::Word(w) => match w {
|
||||
0b000 => Self::AX,
|
||||
0b001 => Self::CX,
|
||||
0b010 => Self::DX,
|
||||
0b011 => Self::BX,
|
||||
0b100 => Self::SP,
|
||||
0b101 => Self::BP,
|
||||
0b110 => Self::SI,
|
||||
0b111 => Self::DI,
|
||||
_ => panic!("Invalid 16bit register ID encountered"),
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -163,10 +270,10 @@ impl SegmentRegister {
|
||||
/// Find the SRegister corresponding to the 8086 bytecode ID
|
||||
pub fn by_id(id: u8) -> Self {
|
||||
match id {
|
||||
0x30 => Self::ES,
|
||||
0x31 => Self::CS,
|
||||
0x32 => Self::SS,
|
||||
0x33 => Self::DS,
|
||||
0x00 => Self::ES,
|
||||
0x01 => Self::CS,
|
||||
0x10 => Self::SS,
|
||||
0x11 => Self::DS,
|
||||
_ => panic!("Invalid segment register ID encountered"),
|
||||
}
|
||||
}
|
||||
@@ -210,13 +317,29 @@ macro_rules! impl_display_and_lowerhex {
|
||||
impl_display_and_lowerhex!(ImmediateByte);
|
||||
impl_display_and_lowerhex!(ImmediateWord);
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
/// ModRM byte can either target a memory location or some register
|
||||
pub enum ModRmTarget {
|
||||
Memory(MemoryIndex),
|
||||
Register(Register),
|
||||
}
|
||||
|
||||
impl std::fmt::Display for ModRmTarget {
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
|
||||
match self {
|
||||
Self::Memory(idx) => write!(f, "{}", idx),
|
||||
Self::Register(reg) => write!(f, "{}", reg),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// A memory index operand is usually created by ModRM bytes or words.
|
||||
/// e.g. [bx+si]
|
||||
#[derive(Debug, Clone)]
|
||||
pub struct MemoryIndex {
|
||||
pub base: Option<Register>,
|
||||
pub index: Option<Register>,
|
||||
pub displacement: Option<Displacement>,
|
||||
pub displacement: Option<OperandSize>,
|
||||
}
|
||||
|
||||
impl fmt::Display for MemoryIndex {
|
||||
@@ -224,18 +347,18 @@ impl fmt::Display for MemoryIndex {
|
||||
match &self.base {
|
||||
Some(base) => match &self.index {
|
||||
Some(index) => match &self.displacement {
|
||||
Some(displacement) => write!(f, "[{}+{}+{}]", base, index, displacement),
|
||||
None => write!(f, "[{}+{}]", base, index),
|
||||
Some(displacement) => write!(f, "[{} + {} + {}]", base, index, displacement),
|
||||
None => write!(f, "[{} + {}]", base, index),
|
||||
},
|
||||
None => match &self.displacement {
|
||||
Some(displacement) => write!(f, "[{}+{}]", base, displacement),
|
||||
None => write!(f, "{}", base),
|
||||
Some(displacement) => write!(f, "[{} + {}]", base, displacement),
|
||||
None => write!(f, "[{} + 0]", base),
|
||||
},
|
||||
},
|
||||
None => match &self.index {
|
||||
Some(index) => match &self.displacement {
|
||||
Some(displacement) => write!(f, "{}+{}", index, displacement),
|
||||
None => write!(f, "{}", index),
|
||||
Some(displacement) => write!(f, "{} + {}", index, displacement),
|
||||
None => write!(f, "[{} + 0]", index),
|
||||
},
|
||||
None => panic!("Invalid MemoryIndex encountered"),
|
||||
},
|
||||
@@ -245,13 +368,13 @@ impl fmt::Display for MemoryIndex {
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
#[allow(dead_code)]
|
||||
/// Displacement for ModRM
|
||||
pub enum Displacement {
|
||||
/// Can be used to encode either byte or word operands
|
||||
pub enum OperandSize {
|
||||
Byte(u8),
|
||||
Word(u16),
|
||||
}
|
||||
|
||||
impl fmt::Display for Displacement {
|
||||
impl fmt::Display for OperandSize {
|
||||
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
||||
match self {
|
||||
Self::Byte(byte) => write!(f, "{}", byte),
|
||||
|
||||
Reference in New Issue
Block a user