diff --git a/src/disasm.rs b/src/disasm.rs index 0337a58..e58fe0c 100644 --- a/src/disasm.rs +++ b/src/disasm.rs @@ -2,7 +2,7 @@ use core::fmt; use std::{fs::File, io::Read, process::exit}; use crate::aout::Aout; -use crate::instructions::{MemoryIndex, ModRmTarget, OperandSize, RegisterId, SegmentRegister}; +use crate::instructions::{MemoryIndex, ModRmTarget, OperandWidth, RegisterId, SegmentRegister}; use crate::{ Args, instructions::{ImmediateByte, ImmediateWord, Instruction, Mnemonic, Register}, @@ -107,7 +107,7 @@ impl Disassembler { /// Parse a single modrm byte, return the resulting MemoryIndex and advance the offset. /// Returns the parsed modrm target and the source register - pub fn parse_modrm_byte(&mut self, size: OperandSize) -> (ModRmTarget, RegisterId) { + pub fn parse_modrm_byte(&mut self, width: OperandWidth) -> (ModRmTarget, RegisterId) { // advance to operand self.offset += 1; let modrm = self.text[self.offset]; @@ -128,27 +128,27 @@ impl Disassembler { 0b00 => { if rm == 0b110 { log::debug!("Additional word during ModRM parsing was read with mod 0."); - displacement = Some(OperandSize::Word(self.parse_word())); + displacement = Some(OperandWidth::Word(self.parse_word())); } else { displacement = None; } } 0b01 => { log::debug!("Additional byte during ModRM parsing was read."); - displacement = Some(OperandSize::Byte(self.parse_byte())) + displacement = Some(OperandWidth::Byte(self.parse_byte())) } 0b10 => { log::debug!("Additional word during ModRM parsing was read."); - displacement = Some(OperandSize::Word(self.parse_word())); + displacement = Some(OperandWidth::Word(self.parse_word())); } 0b11 => { log::debug!("ModRM to reg"); - let target = match size { - OperandSize::Byte(_) => { - ModRmTarget::Register(Register::by_id(OperandSize::Byte(rm))) + let target = match width { + OperandWidth::Byte(_) => { + ModRmTarget::Register(Register::by_id(OperandWidth::Byte(rm))) } - OperandSize::Word(_) => { - ModRmTarget::Register(Register::by_id(OperandSize::Word(rm.into()))) + OperandWidth::Word(_) => { + ModRmTarget::Register(Register::by_id(OperandWidth::Word(rm.into()))) } }; return (target, reg); @@ -204,9 +204,9 @@ impl Disassembler { } /// Match the modrm reg bits to the GPR1 mnemonics. - pub fn modrm_reg_to_mnemonic(reg: u8, target: ModRmTarget, imm: OperandSize) -> Mnemonic { + pub fn modrm_reg_to_mnemonic(reg: u8, target: ModRmTarget, imm: OperandWidth) -> Mnemonic { match imm { - OperandSize::Byte(b) => match reg { + OperandWidth::Byte(b) => match reg { 0b000 => Mnemonic::ADD_Ib(target, ImmediateByte(b)), 0b001 => Mnemonic::OR_Ib(target, ImmediateByte(b)), 0b010 => Mnemonic::ADC_Ib(target, ImmediateByte(b)), @@ -217,7 +217,7 @@ impl Disassembler { 0b111 => Mnemonic::CMP_Ib(target, ImmediateByte(b)), _ => panic!("Illegal GPR1 mnemonic"), }, - OperandSize::Word(w) => match reg { + OperandWidth::Word(w) => match reg { 0b000 => Mnemonic::ADD_Iv(target, ImmediateWord(w)), 0b001 => Mnemonic::OR_Iv(target, ImmediateWord(w)), 0b010 => Mnemonic::ADC_Iv(target, ImmediateWord(w)), @@ -387,14 +387,14 @@ impl Disassembler { // 0x80..=0x83 => panic!("GRP1 not implemented"), 0x80 => { - let (target, reg) = self.parse_modrm_byte(OperandSize::Byte(0)); + let (target, reg) = self.parse_modrm_byte(OperandWidth::Byte(0)); let imm = self.parse_byte(); - Self::modrm_reg_to_mnemonic(reg, target, OperandSize::Byte(imm)) + Self::modrm_reg_to_mnemonic(reg, target, OperandWidth::Byte(imm)) } 0x81 => { - let (target, reg) = self.parse_modrm_byte(OperandSize::Word(0)); + let (target, reg) = self.parse_modrm_byte(OperandWidth::Word(0)); let imm = self.parse_word(); - Self::modrm_reg_to_mnemonic(reg, target, OperandSize::Word(imm)) + Self::modrm_reg_to_mnemonic(reg, target, OperandWidth::Word(imm)) } 0x82 => panic!("Same as 0x80"), 0x83 => panic!("Sign extented GPR1 not yet implemented"), diff --git a/src/disasm_macros.rs b/src/disasm_macros.rs index 1bd359e..378de21 100644 --- a/src/disasm_macros.rs +++ b/src/disasm_macros.rs @@ -2,8 +2,8 @@ /// Generate a byte Opcode for 'normal' ModRM instructions with mem access and a reg macro_rules! modrmb { ($self:ident, $variant:ident) => {{ - let (target, reg) = $self.parse_modrm_byte(OperandSize::Byte(0)); - Mnemonic::$variant(target, Register::by_id(OperandSize::Byte(reg))) + let (target, reg) = $self.parse_modrm_byte(OperandWidth::Byte(0)); + Mnemonic::$variant(target, Register::by_id(OperandWidth::Byte(reg))) }}; } @@ -11,8 +11,8 @@ macro_rules! modrmb { /// Generate a word Opcode for 'normal' ModRM instructions with mem access and a reg macro_rules! modrmv { ($self:ident, $variant:ident) => {{ - let (target, reg) = $self.parse_modrm_byte(OperandSize::Word(0)); - Mnemonic::$variant(target, Register::by_id(OperandSize::Word(reg.into()))) + let (target, reg) = $self.parse_modrm_byte(OperandWidth::Word(0)); + Mnemonic::$variant(target, Register::by_id(OperandWidth::Word(reg.into()))) }}; } @@ -20,7 +20,7 @@ macro_rules! modrmv { /// Generate a word Opcode for 'normal' ModRM instructions with mem access and a segment reg macro_rules! modrms { ($self:ident, $variant:ident) => {{ - let (target, reg) = $self.parse_modrm_byte(OperandSize::Word(0)); + let (target, reg) = $self.parse_modrm_byte(OperandWidth::Word(0)); Mnemonic::$variant(target, SegmentRegister::by_id(reg)) }}; } diff --git a/src/instructions.rs b/src/instructions.rs index d0243bf..404b086 100644 --- a/src/instructions.rs +++ b/src/instructions.rs @@ -204,9 +204,9 @@ pub type RegisterId = u8; #[allow(dead_code)] impl Register { /// Find the register corresponding to the 8086 bytecode ID - pub fn by_id(id: OperandSize) -> Self { + pub fn by_id(id: OperandWidth) -> Self { match id { - OperandSize::Byte(b) => match b { + OperandWidth::Byte(b) => match b { 0b000 => Self::AL, 0b001 => Self::CL, 0b010 => Self::DL, @@ -217,7 +217,7 @@ impl Register { 0b111 => Self::BH, _ => panic!("Invalid 8bit register ID encountered"), }, - OperandSize::Word(w) => match w { + OperandWidth::Word(w) => match w { 0b000 => Self::AX, 0b001 => Self::CX, 0b010 => Self::DX, @@ -339,7 +339,7 @@ impl std::fmt::Display for ModRmTarget { pub struct MemoryIndex { pub base: Option, pub index: Option, - pub displacement: Option, + pub displacement: Option, } impl fmt::Display for MemoryIndex { @@ -369,12 +369,12 @@ impl fmt::Display for MemoryIndex { #[derive(Debug, Clone)] #[allow(dead_code)] /// Can be used to encode either byte or word operands -pub enum OperandSize { +pub enum OperandWidth { Byte(u8), Word(u16), } -impl fmt::Display for OperandSize { +impl fmt::Display for OperandWidth { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { Self::Byte(byte) => write!(f, "{}", byte),