Restructuring into multiple crates and projects
This commit is contained in:
Henrik Böving
275
hm-asm-simulator/src/simulate.rs
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275
hm-asm-simulator/src/simulate.rs
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use crate::generate::insert_label;
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use crate::asm::*;
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use crate::generate::generate_binary;
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use std::collections::HashMap;
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use std::fmt;
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use serde::Serialize;
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize)]
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pub struct StateRegister {
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pub carry: bool,
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pub zero: bool,
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pub negative: bool
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize)]
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pub struct OpcodeInfo {
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pub addr: u8,
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pub content: u8
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}
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#[derive(Copy, Clone, Debug, PartialEq, Eq, Serialize)]
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pub struct State {
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pub step: usize,
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pub clk: bool,
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pub pc: u8,
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pub addr_bus: u8,
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pub data_bus: u8,
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pub ir: u8, // instruction register
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pub dr: u8, // data register
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pub akku: u8,
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pub sr: StateRegister,
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pub opcode_info: Option<OpcodeInfo>
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}
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impl fmt::Display for State {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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writeln!(f, "<tr>")?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.step)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.clk as u8)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.pc)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.addr_bus)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.data_bus)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.ir)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.dr)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">{}</td>", self.akku)?;
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">C: {}, Z: {}, N: {}</td>", self.sr.carry as u8, self.sr.zero as u8, self.sr.negative as u8)?;
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if let Some(opcode_info) = self.opcode_info {
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\">addr: {}, val: {}</td>", opcode_info.addr, opcode_info.content)?;
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} else {
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writeln!(f, "<td style=\"border: 1px solid #000000; padding: 0mm 1.91mm;\"></td>")?;
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}
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writeln!(f, "</tr>")
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}
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}
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pub fn simulate<'a>(instructions: Vec<Instruction<'a>>, max_steps: usize) -> Vec<State> {
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let mut data_memory = generate_binary(instructions.clone()).data_memory;
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let mut labels: HashMap<&str, u8> = HashMap::new();
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let mut states: Vec<State> = Vec::new();
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let mut step: usize = 0;
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let mut clk: bool;
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let mut pc: u8 = 0;
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let mut addr_bus: u8;
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let mut data_bus: u8;
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let mut ir : u8 = 0;
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let mut dr : u8 = 0;
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let mut akku : u8 = 0;
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let mut sr: StateRegister = StateRegister {
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carry: false,
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zero: false,
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negative: false
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};
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for instruction in instructions.iter() {
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match instruction {
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Instruction::NoArgumentInstruction(_, label)
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| Instruction::MemoryLocationInstruction(_, label)
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| Instruction::ConstantArgumentInstruction(_, label)
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| Instruction::ArgumentInstruction(_, label)
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| Instruction::Jump(_, label) => {
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insert_label(&mut labels, label);
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}
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}
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}
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let mut next_pc: Option<u8> = None;
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let mut next_akku = 0;
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let mut next_carry = false;
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let mut next_data_mem_addr: Option<usize> = None;
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let mut next_data_mem_val: Option<u8> = None;
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loop {
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if next_akku != akku {
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next_carry = (next_akku & (1<<4)) != 0;
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}
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if let Some(mut next_pc_value) = next_pc {
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next_pc_value = next_pc_value % 16;
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next_akku = next_akku % 16;
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pc = next_pc_value;
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next_pc = None;
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}
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akku = next_akku;
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if let Some(addr) = next_data_mem_addr {
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data_memory[addr] = next_data_mem_val.unwrap();
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next_data_mem_addr = None;
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next_data_mem_val = None;
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}
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let instruction = if pc as usize > instructions.len() - 1 {
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Instruction::NoArgumentInstruction(NoArgumentInstruction::NOP, None)
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} else {
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instructions[pc as usize]
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};
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let binary_instruction: BinaryInstruction = match instruction {
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Instruction::NoArgumentInstruction(instruction, _) => instruction.into(),
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Instruction::MemoryLocationInstruction(instruction, _) => instruction.into(),
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Instruction::ConstantArgumentInstruction(instruction, _) => instruction.into(),
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Instruction::ArgumentInstruction(instruction, _) => instruction.into(),
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Instruction::Jump(argument, _) => match argument {
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JumpArgument::Location(arg) => BinaryInstruction {
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opcode: 8,
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argument: arg,
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},
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JumpArgument::Label(arg) => {
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if let Some(address) = labels.get(arg) {
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BinaryInstruction {
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opcode: 8,
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argument: *address,
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}
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} else {
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panic!("Tried to JMP to label: {}, which does not exist", arg);
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}
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},
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JumpArgument::MemoryLocation(address) => {
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BinaryInstruction {
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opcode: 12,
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argument: address
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}
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}
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},
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};
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clk = false;
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addr_bus = pc;
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data_bus = data_memory[pc as usize];
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let opcode_info = match instruction {
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Instruction::MemoryLocationInstruction(instruction, _) => {
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match instruction {
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MemoryLocationInstruction::STA(location) => Some(OpcodeInfo{addr: location, content: data_memory[location as usize]}),
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}
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},
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Instruction::ArgumentInstruction(instruction, _) => {
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match instruction {
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ArgumentInstruction::ADD(argument) | ArgumentInstruction::SUB(argument) | ArgumentInstruction::LDA(argument) => match argument {
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Argument::MemoryLocation(location) => Some(OpcodeInfo{addr: location, content: data_memory[location as usize]}),
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_ => None
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}
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}
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},
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Instruction::Jump(JumpArgument::MemoryLocation(location), _) => {
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Some(OpcodeInfo{
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addr: location,
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content: data_memory[location as usize]
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})
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}
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_ => None
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};
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states.push(State{
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step,
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clk,
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pc,
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addr_bus,
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data_bus,
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ir,
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dr,
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akku,
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sr,
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opcode_info
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});
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clk = true;
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sr.carry = next_carry;
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sr.zero = akku == 0 || akku == (1<<4);
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sr.negative = (akku & (1<<3)) != 0;
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dr = binary_instruction.argument;
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ir = binary_instruction.opcode;
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addr_bus = dr;
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match instruction {
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Instruction::NoArgumentInstruction(instruction, _) => match instruction {
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NoArgumentInstruction::NOP => {}
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},
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Instruction::ConstantArgumentInstruction(instruction, _) => match instruction {
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ConstantArgumentInstruction::BRC(arg) if sr.carry => next_pc = Some(pc + arg),
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ConstantArgumentInstruction::BRN(arg) if sr.negative => next_pc = Some(pc + arg),
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ConstantArgumentInstruction::BRZ(arg) if sr.zero => next_pc = Some(pc + arg),
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_ => {}
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},
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Instruction::Jump(arg, _) => match arg {
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JumpArgument::Label(label) => {
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next_pc = Some(*labels.get(label).unwrap());
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addr_bus = *labels.get(label).unwrap();
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},
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JumpArgument::Location(location) => {
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next_pc = Some(location);
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addr_bus = location;
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},
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JumpArgument::MemoryLocation(location) => {
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next_pc = Some(data_memory[location as usize]);
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addr_bus = data_memory[location as usize];
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}
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},
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Instruction::MemoryLocationInstruction(arg, _) => match arg {
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MemoryLocationInstruction::STA(arg) => {
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next_data_mem_addr = Some(arg as usize);
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next_data_mem_val = Some(akku);
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}
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},
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Instruction::ArgumentInstruction(instruction, _) => match instruction {
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ArgumentInstruction::LDA(arg) => match arg {
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Argument::MemoryLocation(location) => next_akku = data_memory[location as usize],
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Argument::Constant(val) => next_akku = val
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},
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ArgumentInstruction::ADD(arg) => match arg {
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Argument::MemoryLocation(location) => next_akku = akku + data_memory[location as usize],
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Argument::Constant(val) => next_akku = akku + val
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},
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ArgumentInstruction::SUB(arg) => match arg {
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Argument::MemoryLocation(location) => next_akku = akku + (data_memory[location as usize] ^ 0b1111) + 1,
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Argument::Constant(val) => next_akku = akku + (val ^ 0b1111) + 1
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}
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}
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}
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data_bus = data_memory[addr_bus as usize];
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if let None = next_pc {
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next_pc = Some(pc + 1);
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}
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states.push(State{
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step,
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clk,
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pc,
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addr_bus,
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data_bus,
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ir,
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dr,
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akku,
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sr,
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opcode_info
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});
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step += 1;
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if step == max_steps {
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break;
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}
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}
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return states;
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}
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