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fix(interpreter): write to correct 8bit regs

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This commit is contained in:
Marco Thomas
2025-07-02 20:58:39 +09:00
parent 4adb975b69
commit 4e23d9419b
2 changed files with 8 additions and 6 deletions
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1
src/interpreter/computer.rs
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@@ -402,6 +402,7 @@ impl Computer {
target: ModRmTarget,
val: ImmediateOperand,
) -> Result<(), InterpreterError> {
log::debug!("Writing {val} into {target}");
match target {
ModRmTarget::Memory(idx) => self.write(val.into(), idx)?,
ModRmTarget::Register(reg) => self.regs.write(reg, val),

13
src/interpreter/register.rs
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@@ -51,6 +51,7 @@ impl Register {
/// Write an [`ImmediateOperand`] to a [`crate::register::Register`].
pub fn write(&mut self, reg: crate::register::Register, val: ImmediateOperand) {
log::debug!("Writing {val:#04x} into {reg}");
match val {
ImmediateOperand::Byte(byte) => match reg {
crate::register::Register::AX => self.ax.lower = byte,
@@ -79,12 +80,12 @@ impl Register {
crate::register::Register::DX => self.dx.write(word),
crate::register::Register::AH => self.ax.upper = high,
crate::register::Register::AL => self.ax.lower = low,
crate::register::Register::BH => self.ax.upper = high,
crate::register::Register::BL => self.ax.lower = low,
crate::register::Register::CH => self.ax.upper = high,
crate::register::Register::CL => self.ax.lower = low,
crate::register::Register::DH => self.ax.upper = high,
crate::register::Register::DL => self.ax.lower = low,
crate::register::Register::BH => self.bx.upper = high,
crate::register::Register::BL => self.bx.lower = low,
crate::register::Register::CH => self.cx.upper = high,
crate::register::Register::CL => self.cx.lower = low,
crate::register::Register::DH => self.dx.upper = high,
crate::register::Register::DL => self.dx.lower = low,
crate::register::Register::DI => self.di = word,
crate::register::Register::SI => self.si = word,
crate::register::Register::BP => self.bp = word,